Entwurf von 50+ Gbps High Speed Serial Links für digitale Systeme

Project Title
50+ Gbps High Speed Serial Link Design for Digital Systems
Principal Investigator
Project Abstract
Industry Project.

High speed serial link design for digital systems is rapidly approaching the 25-50 Gbps data rate and is likely to move beyond in the next decade as can be seen e.g. from the recent 56 Gbps Common Electrical Interface (CEI) initiative of the Optical Internetworking Forum (OIF). With the increase in data rate problems in the areas of signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) will exacerbate and require more attention than before in order to achieve a system that is not threatened in its electrical integrity (see figure below).
In this research project the Institute of Electromagnetic Theory was investigating on behalf of HUAWEI Research Europe the state of the art, the technical issues, and the necessary steps for electrical integrity at such advanced data rates. Specifically the following research areas were addressed in detail

– basic elements of successful link design methodologies,
– necessary CAD tools for link design,
– specific problems and challenges at 50+ Gbps signaling,
– suitable packaging & interconnect structures for 50+ Gbps signaling,
– most important research areas in the near future.

The results were summarized in a White Paper and presented at HUAWEI.