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Mining latency guarantees for RTL designs
Publikationstyp
Conference Paper
Date Issued
2018-07-19
Sprache
English
Author(s)
Institut
TORE-URI
Start Page
68
End Page
73
Citation
The International Symposium on Multiple-Valued Logic: 68-73 (2018)
Contribution to Conference
Publisher DOI
Scopus ID
Guaranteed response times are crucial for control applications. Analyzing the communication latency, i.e., the time needed to transfer data from one end-point to another, in complex on-chip communication architectures is hard. In this paper, we formally define the problem of mining latency guarantees and present a pragmatic approach to mine symbolic conditions that guarantee a latency requirement. The verification problems handled in this approach are inherently multi-valued modeling bit-vectors of the underlying designs. We use the approach to infer the optimal transfer conditions for a bus bridge and an SPI-connection in less than a minute using only up to 5,000 clock cycles of simulation data.
More Funding Information
European Union (IMMORTAL project, grant no. 644905)