High-level modeling of stuck-at faults in approximate multipliers for enhanced test quality

Approximate computing reduces power and improves performance in error-tolerant applications, but testing remains difficult. Traditional fault models are too strict, underscoring the need for accurate prediction of how stuck-at errors, i.e., the effect of stuck-at faults, affect application-level quality. This paper introduces a high-level model for analyzing the impact of stuck-at errors in approximate multipliers, a highly relevant building block in data processing. In particular, the paper proposes decomposing the total error in the defective approximate circuit into approximate and stuck-at errors. The approximate error is known analytically due to the construction of the multiplier. However, the effect of stuck-at faults depends on the bit probabilities and the arithmetic effect of the node on the multiplier output.The high accuracy of the approach is demonstrated by precise gate-level simulations of different truncated multipliers implemented in 40-nm technology.

Subjects

Approximate Computing

Manufacturing Test

Stuck-at Fault Model

Truncate Multiplier

DDC Class

621.38: Electronics, Communications Engineering

621.3: Electrical Engineering, Electronic Engineering

004: Computer Sciences

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High-level modeling of stuck-at faults in approximate multipliers for enhanced test quality