Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained Devices

Publikationstyp
Conference Paper
Date Issued
2023
Sprache
English
Author(s)
Jahnke, Marek
Smart Sensors E-EXK3
Bublitz, Lucas
Smart Sensors E-EXK3
Kulau, Ulf
Smart Sensors E-EXK3
TORE-URI
https://hdl.handle.net/11420/44696
Citation
IEEE Nordic Circuits and Systems Conference (NorCAS 2023)
Contribution to Conference
IEEE Nordic Circuits and Systems Conference, NorCAS 2023
Publisher DOI
10.1109/NorCAS58970.2023.10305479
Scopus ID
2-s2.0-85179505491
ISBN of container
9798350337570
In this paper, an extensive analysis of the resource-efficient PicoRV32 softcore, which implements the RISC-V instruction set, is performed. The focus of the analysis is on performance, energy efficiency and resource utilization. For this, both CoreMark and Embench are implemented as benchmark tools.In contrast to previous evaluations, a resource-constrained target platform (Low Power (LP) FPGA) is explicitly used for the evaluation, to demonstrate the applicability on very small embedded systems. Furthermore, all configurations of the softcore are investigated, which helps in the estimation and subsequent configuration of the softcore and reveals significant bottlenecks like memory interface.
Subjects
Benchmark
LP FPGA
Resource-Constrained Devices
RISC-V
Softcore
DDC Class
620: Engineering