DC FieldValueLanguage
dc.contributor.authorSaidi, Selma-
dc.contributor.authorSyring, Alexander-
dc.date.accessioned2019-03-13T14:59:46Z-
dc.date.available2019-03-13T14:59:46Z-
dc.date.issued2019-01-04-
dc.identifier.citationProceedings - Real-Time Systems Symposium (2018-December): 350-360 (2019-01-04)de_DE
dc.identifier.isbn978-153867907-4de_DE
dc.identifier.issn1052-8725de_DE
dc.identifier.urihttp://hdl.handle.net/11420/2160-
dc.description.abstractThe integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity. © 2018 IEEE.en
dc.language.isoende_DE
dc.relation.ispartofProceedings - Real-Time Systems Symposiumde_DE
dc.titleExploiting Locality for the Performance Analysis of Shared Memory Systems in MPSoCsde_DE
dc.typeinProceedingsde_DE
dc.type.dinicontributionToPeriodical-
dcterms.DCMITypeText-
tuhh.abstract.englishThe integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity. © 2018 IEEE.de_DE
tuhh.publisher.doi10.1109/RTSS.2018.00050-
tuhh.publication.instituteEingebettete Systeme E-13de_DE
tuhh.type.opusInProceedings (Aufsatz / Paper einer Konferenz etc.)-
tuhh.institute.germanEingebettete Systeme E-13de
tuhh.institute.englishEingebettete Systeme E-13de_DE
tuhh.gvk.hasppnfalse-
dc.type.drivercontributionToPeriodical-
dc.type.casraiConference Paper-
tuhh.container.startpage350de_DE
tuhh.container.endpage360de_DE
item.languageiso639-1en-
item.grantfulltextnone-
item.openairetypeinProceedings-
item.cerifentitytypePublications-
item.creatorOrcidSaidi, Selma-
item.creatorOrcidSyring, Alexander-
item.fulltextNo Fulltext-
item.creatorGNDSaidi, Selma-
item.creatorGNDSyring, Alexander-
item.openairecristypehttp://purl.org/coar/resource_type/c_5794-
crisitem.author.deptEingebettete Systeme E-13-
crisitem.author.deptEingebettete Systeme E-13-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik-
crisitem.author.parentorgStudiendekanat Elektrotechnik, Informatik und Mathematik-
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