|Publisher DOI:||10.1109/ISMVL.2018.00020||Title:||Mining latency guarantees for RTL designs||Language:||English||Authors:||Malburg, Jan
|Issue Date:||19-Jul-2018||Source:||Proceedings of The International Symposium on Multiple-Valued Logic (2018-May): 68-73 (2018-07-19)||Journal or Series Name:||Proceedings of The International Symposium on Multiple-Valued Logic||Abstract (english):||Guaranteed response times are crucial for control applications. Analyzing the communication latency, i.e., the time needed to transfer data from one end-point to another, in complex on-chip communication architectures is hard. In this paper, we formally define the problem of mining latency guarantees and present a pragmatic approach to mine symbolic conditions that guarantee a latency requirement. The verification problems handled in this approach are inherently multi-valued modeling bit-vectors of the underlying designs. We use the approach to infer the optimal transfer conditions for a bus bridge and an SPI-connection in less than a minute using only up to 5,000 clock cycles of simulation data.||URI:||http://hdl.handle.net/11420/2630||ISBN:||978-153864463-8||ISSN:||0195-623X||Institute:||Eingebettete Systeme E-13||Type:||InProceedings (Aufsatz / Paper einer Konferenz etc.)||Funded by:||European Union (IMMORTAL project, grant no. 644905)|
|Appears in Collections:||Publications without fulltext|
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