Yu, QiangQiangYuLi, QiangQiangLi2025-12-152025-12-152025-11-26Electronics Letters 61 (1): e70479 (2025)https://hdl.handle.net/11420/59600Pipelined analogue-to-digital converters suffer from inter-stage gain errors and inter-stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial-based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.en0013-5194Electronics letters20251IEThttps://creativecommons.org/licenses/by-nc-nd/4.0/analogue–digital conversioncalibrationCMOS integrated circuitsTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringA low-cost and low-latency inter-stage nonlinearity error calibration algorithm for pipelined ADCsLetter to the Editorhttps://doi.org/10.15480/882.1628810.1049/ell2.7047910.15480/882.16288Letter to the Editor