Saidi, SelmaSelmaSaidiSyring, AlexanderAlexanderSyring2019-03-132019-03-132018-12Real-Time Systems Symposium: 350-360 (2018)http://hdl.handle.net/11420/2160The integration trend and increased required computing power is driving the advent of common embedded consumer devices like MPSoCs platforms in the safety critical domain. MPSoCs often feature a shared tightly-coupled memory system where a careful management of data storage and transfers is a key enabler for performance. However, providing real-time guarantees for these platforms is extremely challenging as they rely on exploiting data locality to improve average latencies in shared-memory architectures. This effect is often disregarded by existing real-time analysis approaches which furthermore often focus solely on a single component of the memory system. In this paper, we propose a framework for the timing analysis of shared memory systems composed of on-chip scratchpad memories, off-chip DRAMs and DMA engines. The analysis captures the effect on the performance of the system of the locality of accesses, their interleaving and granularity. © 2018 IEEE.enConference Paper10.1109/RTSS.2018.00050Other