Shamookh, M.M.ShamookhAshok, A.A.AshokZambanini, A.A.ZambaniniGeläschus, Anton UlrichAnton UlrichGeläschusGrewing, C.C.GrewingBahr, AndreasAndreasBahrVan Waasen, S.S.Van Waasen2025-01-072025-01-072024-0720th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2024)9798350351927https://tore.tuhh.de/handle/11420/53017A high voltage (HV) that is usually not available in modern nodes is required to form memristors. A scalable implementation requires the HV to be generated on chip and this work proposes such a generator. In a 28 nm CMOS process, a three-stage charge pump (CP)) is designed in the absence of HV transistors. For the HfO2 based memristor electroforming (EF), a developed CP runs with an efficiency of 46.5% at an output voltage of 3.35 V and a load current of 184.9 μ A from a 1.8 V supply. The optimum design strategy for a cross-coupled charge pump (CC-CP) is explained for a low ripple <6 mV, while at the same time ensuring lower capacitor value and high reliability. The results of an over-voltage analytical investigation have important ramifications for lowering the overall area without compromising output voltage or CP efficiency. Monte Carlo simulation for 200 samples were also performed to verify the design's robustness. However, the proposed design can be readily extended to any memristor application or material, thereby paving the way for the integration of fully integrated chips (ICs) for memristor EF in smaller technology nodes.enelectroforming (EF) | ESD | high voltage generator | memristor | neuromorphic computing | rippleConference Paper10.1109/SMACD61181.2024.10745430Conference Paper