Baesler, MalteMalteBaeslerVoigt, Sven-OleSven-OleVoigt2018-03-092018-03-092013Malte Baesler and Sven-Ole Voigt, “Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, Article ID 453173, 16 pages, 2013. doi:10.1155/2013/453173http://tubdok.tub.tuhh.de/handle/11420/1577Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binaryand decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binaryand decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.en1687-72092013Volume 2013 16 pagesArticle ID 45317316 pagesHindawi Publishing Corporationhttps://creativecommons.org/licenses/by/3.0/IngenieurwissenschaftenJournal Article2018-02-26Copyright © 2013 Malte Baesler and Sven-Ole Voigt. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.urn:nbn:de:gbv:830-882.0395210.15480/882.157411420/157710.1155/2013/45317310.15480/882.1574Journal Article