Göttsche, RalfRalfGöttscheSchulz, T.T.SchulzBrüls, N.N.BrülsKrautschneider, WolfgangWolfgangKrautschneider2024-06-252024-06-252004-12-01In: Proceeding of the 34th European Solid-State Device Research Conference, 2004, ESSDERC 2004 : 21 - 23 Sept. 2004, [Leuven, Belgium]. - Piscataway, NJ : IEEE Operations Center, 2004. - S.385-3880780384784https://hdl.handle.net/11420/48037A simulation framework has been developed for fast and accurate calculation of MOS transistor characteristics. It is based on an optimized table model, so that it can be run solely using experimental or simulated I-V data, i.e. without any time-consuming determination of model parameters. This model is designed in a very flexible manner, thus it can be used for advanced MOS structures, such as Double-Gate and FinFET transistors, as well. By this means, it facilitates the integration of a parameterized device technology directly into a conventional design flow to qualify circuits in the design space. ©2004 IEEE.enTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference PaperConference Paper