Shamookh, MuhammadMuhammadShamookhAshok, ArunArunAshokZambanini, AndréAndréZambaniniGeläschus, Anton UlrichAnton UlrichGeläschusGrewing, ChristianChristianGrewingBahr, AndreasAndreasBahrWaasen, Stefan vanStefan vanWaasen2025-02-272025-02-272024-1131st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024979-8-3503-7720-0https://hdl.handle.net/11420/54510The process of electroforming (EF) a memristor involves setting the channel resistance via current compliance Icc. This EF phase varies in duration based on the EF voltage VEF, requiring high voltage (HV) as a trade-off with EF time. To achieve CMOS-memristor scalable co-integration, on-chip HV-generation is essential. This study presents an analytical design approach for a proposed three-stage charge pump (CP), focusing on achieving optimal balance among efficiency, output ripple, Icc, and minimal capacitor. The proposed 28 nm three-stage CP requires 1.8 V IO devices for 3.35 V output voltage and achieves 46.5% voltage conversion ratio (VCR). It includes a ripple reduction stage to ensure a ripple below 6mV with high current demands of up to 200 μ A, without an additional space for over-voltage protection within the CP core. Corners and Monte Carlo simulations are conducted to validate the robustness of the design. By eliminating HV-transistors or multi-phase clocks, the design effectively reduces system costs, enhancing the efficiency and scalability of emerging neuromorphic systems.encharge pump | current compliance | electroforming (EF) | electroforming time | high voltage generator | memristor | neuromor-phic computing | output rippleTechnology::600: TechnologyConference Paper10.1109/ICECS61496.2024.10848531Conference Paper