Rimolo-Donadio, RenatoRenatoRimolo-DonadioDuan, XiaominXiaominDuanKwark, Young HoonYoung HoonKwarkGu, XiaoxiongXiaoxiongGuBaks, Christian W.Christian W.BaksMüller, SebastianSebastianMüllerWinkel, Thomas MichaelThomas MichaelWinkelStrach, ThomasThomasStrachShan, LeiLeiShanHarrer, HubertHubertHarrerSchuster, ChristianChristianSchuster2020-06-172020-06-172013Where chipheads connect : DesignCon 2013 ; Santa Clara, California, USA, 28 - 31 January 2013 / [UBM Electronics]. - Red Hook, NY : CurranDesignCon. - Vol. 1 (2013): Seite 807-831http://hdl.handle.net/11420/6353The modeling of multiple high-speed chip-to-chip communication links over first (IC package) and second (board) level interconnects is addressed in this paper for data rates up to 28 Gb/s with model-to-hardware correlation. The suggested methodology is based on a bottom-up hybrid approach combining semi-analytical and numerical models, which are able to simultaneously consider the signal and power integrity domains and allow the incorporation of power noise models for the time domain link simulation. The required model complexity and the design space for passive interconnects are explored by analyzing diverse via and channel configurations.enIngenieurwissenschaftenConference PaperOther