Fischer, ThiloThiloFischerFalk, HeikoHeikoFalk2024-07-042024-07-042024Design, Automation and Test in Europe Conference and Exhibition, DATE 2024979-8-3503-4859-0https://hdl.handle.net/11420/48193When sharing a cache between multiple cores, the inter-core interference has to be considered in the worst-case execution time (WCET) analysis. Current interference models are overly pessimistic or not applicable to preemptively scheduled systems. We propose a novel technique to model interference in a preemptive system to classify accesses as cache hits or potential misses. We account for inter-core interference by considering the potential execution scenarios on the interfering core and find the worst-case interference pattern. The resulting access classifications are then used to compute the cache-related preemption delay. Our evaluation shows that the proposed analysis significantly increases the cache hit classifications, reduces WCET on average by up to 11.7%, and reduces worst-case response times on average by up to 15.4% compared to the existing classification technique.enComputer Science, Information and General Works::005: Computer Programming, Programs, Data and SecurityTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference Paper10.23919/date58400.2024.10546581Conference Paper