Vega-Castillo, PaolaPaolaVega-CastilloKrautschneider, WolfgangWolfgangKrautschneider2024-06-262024-06-262005Proceedings of SPIE - The International Society for Optical Engineering Volume 5837 pt. II, pp. 953 - 960, art. no. 110 (2005)https://hdl.handle.net/11420/48082A PMOS-based non-volatile memory cell fully compatible with standard CMOS fabrication processes is presented. It consists of a PMOS access transistor in series with a PMOS transistor whose gate is left floating. The cell configuration eliminates the requirement of a control gate, and therefore can be fabricated without using double poly gates. The cell saves area compared to other single poly non-volatile memory cells based on CMOS approaches, which require both NMOS and PMOS transistors. It also avoids the risk of latch-up. The cells were fabricated using a 350nm standard CMOS process. The programming mechanism of the cell is hot electron injection. The programming operation can be performed at programming voltages as low as |Vds|=4.5V. The cell can be used as a low voltage OTP and provides a very cheap alternative to integrate OTPs in CMOS ICs without any modification of the fabrication process.enCMOS compatibleLow voltageOTPSingle-polyTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference Paper10.1117/12.607964Conference Paper