Pereira-Arroyo, RobertoRobertoPereira-ArroyoAlvarado-Moya, PabloPabloAlvarado-MoyaKrautschneider, WolfgangWolfgangKrautschneider2024-06-212024-06-212007IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), Porto Alegre, Brazil, 2007, pp. 81-85978-0-7695-2896-0https://hdl.handle.net/11420/47991In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multiobjective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented. © 2007 IEEE.enDesign space explorationGenetic algorithmsMOS current mode logic (MCML)Multi-objective optimizationPareto frontTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference Paper10.1109/ISVLSI.2007.38Conference Paper