Meza Cuevas, Mario AlbertoMario AlbertoMeza CuevasSchröder, DietmarDietmarSchröderKrautschneider, WolfgangWolfgangKrautschneider2024-05-242024-05-242014Middle East Conference on Biomedical Engineering (MECBME), 2014, Doha, Qatar, 17-20 Feb. 2014978-1-4799-4798-0978-1-4799-4799-7https://hdl.handle.net/11420/47587In this work a 130 nm CMOS 64 channel neural stimulator is presented, which is scalable by connecting it in a daisy chain configuration, for applications requiring larger number of stimulation sites, as it is of interest for retinal implants with improved resolution. Each channel is composed of a hybrid architecture current steering 8 bit DAC, enabling the low power consumption and high channel integration on a small chip area. Besides, the DAC allows stimulating with several waveforms in order to save stimulation energy. An on-chip module was implemented to control galvanostatic deposition of PEDOT on the electrodes. A schema is presented to avoid the residual charge due to cross electrode stimulation and process mismatch. © 2014 IEEE.enTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference Paper10.1109/MECBME.2014.6783218Conference Paper