Lucas, JanJanLucasLal, SohanSohanLalJuurlink, Ben H. H.Ben H. H.Juurlink2022-04-202022-04-202018-03Design, Automation and Test in Europe Conference and Exhibition (DATE 2018)http://hdl.handle.net/11420/12318GDDR5 and DDR4 memories use data bus inversion (DBI) coding to reduce termination power and decrease the number of output transitions. Two main strategies exist for encoding data using DBI: DBI DC minimizes the number of outputs transmitting a zero, while DBI AC minimizes the number of signal transitions. We show that neither of these strategies is optimal and reduction of interface power of up to 6% can be achieved by taking both the number of zeros and the number of signal transitions into account when encoding the data. We then demonstrate that a hardware implementation of optimal DBI coding is feasible, results in a reduction of system power and requires only an insignificant additional die area.enData bus inversionDDR4GDDR5power consumptiontermination powerConference Paper10.23919/DATE.2018.8342169Other