Rahman, AbdurAbdurRahmanFey, GörschwinGörschwinFey2024-12-112024-12-112024-092024 IEEE 37th International System-on-Chip Conference (SOCC)979-8-3503-7756-9979-8-3503-7757-6https://hdl.handle.net/11420/52445With the emergence of Large Language Models (LLMs), there has been a growing interest in harnessing their potential applications beyond traditional natural language processing tasks. One such application is hardware design validation. This paper presents a comprehensive evaluation of LLMs in design validation tasks. In design validation, it is essential to analyze the designs and crafting appropriate testbenches for them. We evaluate the ability to recognize hardware descriptions as well as the ability to generate testbenches for those designs. We present evaluation methodology and benchmarks to evaluate these tasks. Experiments were conducted with four prominent LLMs and designs ranging from small arithmetic block up to a small MIPS CPU. The results demonstrate promising performance for a limited complexity threshold.endesign | large language model | validationTechnology::600: TechnologyConference Paper10.1109/SOCC62300.2024.10737717Conference Paper