Solis-Arbustini, Johan-RobertoJohan-RobertoSolis-ArbustiniMendoza Ponce, Pablo DanielPablo DanielMendoza PonceKrautschneider, WolfgangWolfgangKrautschneiderKuhl, MatthiasMatthiasKuhl2020-05-152020-05-152020-02Latin American Symposium on Circuits and Systems, LASCAS: 9068978 (2020-02)http://hdl.handle.net/11420/6149This work presents an incremental 2nd-order sigma delta using a single operational transconductance amplifier. This design provides a good trade-off between time conversion, high bit resolution, power consumption and area utilization for a pressure sensing reading interface. The modulator, designed in 180 nm CMOS technology, has been optimized for low area utilization, occupying only 0.058 mm2. Post-layout simulations were performed showing a resolution of 150 μV while consuming 120 μW and 460 fJ/conv. The system has a resolution of 16 bits, a bandwidth of 2 kHz, an oversampling ratio of 512 and a sampling frequency of 2 MHz.enCMOSIncremental analog-to-digital converter (IADC)low-arealow-powersigma delta modulationConference Paper10.1109/LASCAS45839.2020.9068978Other