Yu, QiangQiangYuLi, QiangQiangLi2026-06-052026-06-052026-05-25Electronics Letters 62 (1): e70603 (2026)https://hdl.handle.net/11420/63309This letter presents a 10-bit 5-GS/s time-interleaved (TI) pipelined successive-approximation-register (SAR) analogue-to-digital converter (ADC). By utilizing a full-speed passive track-and-hold circuit (T/H), pre-quantization can be performed in parallel, alleviating the timing constraint in the first stage. The chopped switches in the passive T/H enable input-independent background offset calibration for comparators and residue amplifiers. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 51.8-dB SNDR and 67.9-dB SFDR at the Nyquist input.en0013-5194Electronics letters20261The Institution of Engineering and Technology (IET)https://creativecommons.org/licenses/by-nc-nd/4.0/analogue circuitsanalogue-digital conversioncalibrationTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic Engineering::621.38: Electronics, Communications EngineeringA 10-b 5-GS/s passive T/H assisted time-interleaved pipelined-SAR ADC with pre-quantization and background offset calibrationJournal Articlehttps://doi.org/10.15480/882.1723410.1049/ell2.7060310.15480/882.17234