Fischer, ThiloThiloFischerFalk, HeikoHeikoFalk2023-08-042023-08-042023Design, Automation and Test in Europe (DATE 2023)978-398192637-8https://hdl.handle.net/11420/42518We propose a novel analysis approach for shared LRU caches to classify accesses as definitive cache hits or potential misses. In this approach inter-core cache interference is modelled as an event stream. Thus, by analyzing the timing between subsequent accesses to a particular cache block, it is possible to bound the inter-core interference. This perspective allows us to classify accesses as cache hits or potential misses using a data-flow analysis. We compare the performance of the presented approach to a partitioning of the shared cache.enmulti-coreshared cacheWCET analysisTechnologyConference Paper10.23919/DATE56975.2023.10137034Conference Paper