Domdey, AndreasAndreasDomdeyHafkemeyer, Kristian M.Kristian M.HafkemeyerSchröder, DietmarDietmarSchröderKrautschneider, WolfgangWolfgangKrautschneider2024-06-192024-06-192009-01NORCHIP, 2009 : [Trondheim, Norway], 16 - 17 Nov. 2009. - Art. no. 5397843 (2009)978-1-4244-4310-9978-1-4244-4311-6https://hdl.handle.net/11420/47924In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to stress up to 4k DUTs under same conditions. Several array test structures with different perimeters as well as areas integrated on one chip are available. Low-cost automated test systems allow for gate voltage stress experiments on a large scale with numerous array test structures in parallel. Experimental results are shown. ©2009 IEEE.enTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringConference Paper10.1109/NORCHP.2009.5397843Conference Paper