Hafkemeyer, Kristian M.Kristian M.HafkemeyerDomdey, AndreasAndreasDomdeySchröder, DietmarDietmarSchröderKrautschneider, WolfgangWolfgangKrautschneider2024-06-182024-06-182012-05-11IEEE Transactions on Semiconductor Manufacturing 25 (2): 130-135 (2012-05)https://hdl.handle.net/11420/47901An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation. © 2012 IEEE.en0894-650720122130135IEEEArraysdielectric breakdownMOS devicessemiconductor device reliabilityTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringJournal Article10.1109/TSM.2011.2181647Journal Article