Yu, QiangQiangYuZhu, ZhengZhengZhuZhang, LuluLuluZhangHuang, QinQinHuangFeng, YaoYaoFengLiang, ChaoChaoLiangHu, BiaoBiaoHuDu, LingLingDuYang, RongbinRongbinYangWu, ShuangyiShuangyiWuLi, QiangQiangLi2025-12-172025-12-172025-12-02IEEE Solid State Circuits Letters 9: 9-12 (2026)https://hdl.handle.net/11420/60292This letter presents a 14-bit 500-MS/s 3-stage pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching problem between the input buffer and the sampling circuit. Second, a reference charge neutralization minimizes reference ripple. Finally, a digital harmonic correction is realized with a low-cost and low-latency LUT. Fabricated in a 28-nm CMOS process, the prototype ADC achieves 64.6-dB SNDR and 82.6-dB SFDR at Nyquist.en2573-96032025912IEEE2b/cycleanalog-to-digital converter (ADC)linearity enhancement techniquespipelined-successive-approximation-register (SAR) ADCTechnology::600: TechnologyTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringJournal Article10.1109/LSSC.2025.3639322Journal Article