Stylianopoulos, CharalamposCharalamposStylianopoulosAlmgren, MagnusMagnusAlmgrenLandsiedel, OlafOlafLandsiedelPapatriantafilou, MarinaMarinaPapatriantafilou2025-02-072025-02-072017-08Proceedings of the 46th International Conference on Parallel Processing, ICPP 2017: 8025321, 472-482978-1-5386-1042-8978-1-5386-1043-5https://hdl.handle.net/11420/53902Pattern matching is a key building block of Intrusion Detection Systems and firewalls, which are deployed nowadays on commodity systems from laptops to massive web servers in the cloud. In fact, pattern matching is one of their most computationally intensive parts and a bottleneck to their performance. In Network Intrusion Detection, for example, pattern matching algorithms handle thousands of patterns and contribute to more than 70% of the total running time of the system.In this paper, we introduce efficient algorithmic designs for multiple pattern matching which (a) ensure cache locality and (b) utilize modern SIMD instructions. We first identify properties of pattern matching that make it fit for vectorization and show how to use them in the algorithmic design. Second, we build on an earlier, cache-aware algorithmic design and we show how cache-locality combined with SIMD gather instructions, introduced in 2013 to Intel's family of processors, can be applied to pattern matching. We evaluate our algorithmic design with open data sets of real-world network traffic:Our results on two different platforms, Haswell and Xeon-Phi, show a speedup of 1.8x and 3.6x, respectively, over Direct Filter Classification (DFC), a recently proposed algorithm by Choi et al. for pattern matching exploiting cache locality, and a speedup of more than 2.3x over Aho-Corasick, a widely used algorithm in today's Intrusion Detection Systems.enGather | Pattern matching | SIMD vectorizationTechnology::600: TechnologyConference Paper10.1109/ICPP.2017.56Conference Paper