Chen, TianyuTianyuChenZhuang, HaoyuHaoyuZhuangHe, YajuanYajuanHeLi, QiangQiangLi2025-12-162025-12-162025IEEE Transactions on Circuits and Systems II Express Briefs: (2025)https://hdl.handle.net/11420/60298This brief proposes a charge-domain analog Compute-In-Memory (CIM) architecture based on multi-bit SRAM. The proposed structure consists of a 64×64 10T1C SRAM array, which can perform 1024 MAC operations between 4-bit signed input and weight within a single clock cycle. An 8-bit Analog-to-Digital Converter (ADC) is employed for quantization, converting the analog Multiply-Accumulate (MAC) results into 8-bit digital signals for output. The ADC module adopts capacitor array multiplexing, pseudo-differential sampling with double-terminal flipping method and matching layout designing to save area. The proposed circuit is implemented in 28nm process which operates at a supply voltage of 0.8V. It achieves an energy efficiency of 184 TOPS/W and an area efficiency of 7.3 TOPS/mm², and reaches an accuracy of 86.9% in the training on CIFAR-10 dataset. When compared with other works, the highlight of this work is the highest energy efficiency and the highest area efficiency on 4-bit input and weight precision normalized to 28nm.en1558-37912025IEEECharge-DomainCompute-In-Memory (CIM)Deep Neural Networks (DNNs)SRAMSuccessive Approximation Register (SAR) ADCTechnology::600: TechnologyTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringJournal Article10.1109/TCSII.2025.3639896Journal Article