Baesler, MalteMalteBaeslerTeufel, ThomasThomasTeufel2021-01-252021-01-252009-12-01ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs: 5382019, 6-11 (2009-12-01)http://hdl.handle.net/11420/8563Decimal Floating Point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation and a BCD-4221 Carry Save Adder reduction tree [1]. Furthermore, we extend the multiplier with an accurate scalar product unit in order to provide an important operation with smallest possible rounding error as proposed in [2]. Finally the design is implemented and tested on a Xilinx Virtex-II Pro FPGA platform.enAccurate scalar productDecimal multiplierFloating pointFPGAIEEE 754-2008InformatikMathematikConference Paper10.1109/ReConFig.2009.17Other