Wang, LinfangLinfangWangTerrill, CalebCalebTerrillStark, MaximilianMaximilianStarkLI, ZongwangZongwangLIChen, SeanSeanChenHulse, ChesterChesterHulseKuo, CalvinCalvinKuoWesel, Richard D.Richard D.WeselBauch, GerhardGerhardBauchPitchumani, RekhaRekhaPitchumani2022-05-122022-05-122022-02-07IEEE Transactions on Communications 70 (4): 2213-2226 (2022-04-01)http://hdl.handle.net/11420/12590This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.en1558-08572022422132226IEEEFPGAHardware efficiencyLayered decodingLDPC decoderLow bit width decodingInformatikJournal Article10.1109/TCOMM.2022.3149913Other