Architecture of a pipelined datapath coarse-grain reconfigurable coprocessor array

Hanoun, AbdulrahmanAbdulrahmanHanounManteuffel, HenningHenningManteuffelMayer-Lindenberg, FritzFritzMayer-LindenbergGaljan, WjatscheslawWjatscheslawGaljan2024-09-262024-09-262007IEEE International Conference on Signal Processing and Communications (ICSPC 2007)1-4244-1236-6978-1-4244-1236-5https://hdl.handle.net/11420/49268In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13 technologies and subjected to a group of benchmarks. The resulting delay area products showed that dual-ALU cells have about 50% smaller area-delay product than the single-ALU cell has.enCoarse-grainCoprocessorDistributed arithmeticPipelineReconfigurableTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringArchitecture of a pipelined datapath coarse-grain reconfigurable coprocessor arrayConference Paper10.1109/ICSPC.2007.4728448Conference Paper