Jahnke, MarekMarekJahnkeBublitz, LucasLucasBublitzKulau, UlfUlfKulau2023-12-192023-12-192023IEEE Nordic Circuits and Systems Conference (NorCAS 2023)9798350337570https://hdl.handle.net/11420/44696In this paper, an extensive analysis of the resource-efficient PicoRV32 softcore, which implements the RISC-V instruction set, is performed. The focus of the analysis is on performance, energy efficiency and resource utilization. For this, both CoreMark and Embench are implemented as benchmark tools.In contrast to previous evaluations, a resource-constrained target platform (Low Power (LP) FPGA) is explicitly used for the evaluation, to demonstrate the applicability on very small embedded systems. Furthermore, all configurations of the softcore are investigated, which helps in the estimation and subsequent configuration of the softcore and reveals significant bottlenecks like memory interface.enBenchmarkLP FPGAResource-Constrained DevicesRISC-VSoftcoreEngineering and Applied OperationsConference Paper10.1109/NorCAS58970.2023.10305479Conference Paper