Hardock, AndreasAndreasHardockDahl, DavidDavidDahlBrüns, Heinz-DietrichHeinz-DietrichBrünsSchuster, ChristianChristianSchuster2020-09-012020-09-012015-09-02IEEE Workshop on Signal and Power Integrity, SPI : 7237396 (2015-09-02)http://hdl.handle.net/11420/7198This paper presents an efficient computation of the static capacitance related to external fringing fields of vias (plated through holes) in printed circuit boards (PCBs). For this purpose, a numerical approach based on an integral equation for the surface charge density of axially symmetric geometries is used. The proposed method is validated with a commercial quasi-static tool. The capacitance model is applied to the modeling of typical PCB via stubs in the frequency range between 1 and 40 GHz. The results from the physics-based modeling are confirmed with a full-wave solver.enparasitic capacitance extractionprinted circuit board (PCB)Via modelingConference Paper10.1109/SaPIW.2015.7237396Other