Biereigel, StefanStefanBiereigelKulis, SzymonSzymonKulisMoreira, Paulo Rodrigues SimoesPaulo Rodrigues SimoesMoreiraKölpin, AlexanderAlexanderKölpinLeroux, PaulPaulLerouxPrinzie, JeffreyJeffreyPrinzie2021-11-172021-11-172021-11-10Electronics 10 (22): 2741 (2021)http://hdl.handle.net/11420/10961This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>62</mn><mo>.</mo><mn>5</mn></mrow></semantics></math></inline-formula><inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula>/<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="normal">m</mi></semantics></math></inline-formula><inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="normal">g</mi></semantics></math></inline-formula> as well as tolerance to the Total Ionizing Dose (TID) exceeding <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>1</mn><mo>.</mo><mn>5</mn></mrow></semantics></math></inline-formula><inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="normal">G</mi></semantics></math></inline-formula><inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>rad</mi></semantics></math></inline-formula>. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40–320 or at data rates from 40Mbps–320Mbps and displays a jitter performance of 520 with a power dissipation of only 11 and an FOM of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>235</mn></mrow></semantics></math></inline-formula> .This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5MeVcm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40MHz to 320MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11mW and an FOM of −235 dB.en2079-9292202122Multidisciplinary Digital Publishing Institutehttps://creativecommons.org/licenses/by/4.0/All-DigitalPLLCDRSingle-Event Effectsradiation hardeningTechnikIngenieurwissenschaftenJournal Article2021-11-1110.15480/882.391010.3390/electronics1022274110.15480/882.3910Other