Baesler, MalteMalteBaeslerVoigt, Sven-OleSven-OleVoigtTeufel, ThomasThomasTeufel2018-03-092018-03-092010-12-23International Journal of Reconfigurable Computing, vol. 2010, Article ID 357839, 13 pageshttp://tubdok.tub.tuhh.de/handle/11420/1578Decimal Floating Point operations are important for applications that cannot tolerate errors from conversionsbetween binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, wepresent a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is basedon BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipelinestages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unitfor IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unitand migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accuratescalar product unit's latency even by a factor of five.Decimal Floating Point operations are important for applications that cannot tolerate errors from conversionsbetween binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, wepresent a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is basedon BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipelinestages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unitfor IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unitand migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accuratescalar product unit's latency even by a factor of five.en1687-72092010Article ID 357839, 13 pagesHindawi Publishing Corporationhttps://creativecommons.org/licenses/by/3.0/decimal floating point operationIngenieurwissenschaftenJournal Article2018-02-26Copyright © 2010 Malte Baesler et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.urn:nbn:de:gbv:830-882.0397810.15480/882.157511420/157810.1155/2010/35783910.15480/882.1575Journal Article