Voigt, Sven-OleSven-OleVoigtBaesler, MalteMalteBaeslerTeufel, ThomasThomasTeufel2021-01-212021-01-212010-08-05Journal of Systems Architecture 11 (56): 561-576 (2010-11-01)http://hdl.handle.net/11420/8534In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.en1383-7621201011561576ElsevierDataflow architectureDigital signal processingHardware reconfigurationMulti-FPGA platformParallel FFTInformatikJournal Article10.1016/j.sysarc.2010.07.010Other