Ghasempouri, TaraTaraGhasempouriMalburg, JanJanMalburgDanese, AlessandroAlessandroDanesePravadelli, GrazianoGrazianoPravadelliFey, GörschwinGörschwinFeyRaik, JaanJaanRaik2020-01-022020-01-022019-10IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC: 8920331 (2019-10)http://hdl.handle.net/11420/4249Several approaches exist for specification mining of hardware designs, both at the RTL and system levels (e.g, TLM). These approaches mine assertions that specify the behavior of the design. Some of the techniques require the source code itself while others can extract assertions directly from simulation traces. The performance of some approaches is highly dependent on the number of simulation traces/use cases while there exist approaches which can extract assertions from a limited number of simulation traces. Apart from this aspect, the core of each assertion miner is different from the other ones. Some use expression templates to define assertions while some are based on the static analysis or information flow analysis. Unfortunately, it has been rarely considered which of the current approaches are more effective in describing functionality of particular types of designs. Thus, in this work, we analyze assertion miners which are template based and dynamic dependency graph based, respectively. We generate assertions from both approaches. The evaluation considers fault analysis on both assertion sets of extracted assertions. Moreover, both sets are combined and fault analysis has been applied on them. Experimental results show that each set approximately detects the same number of faults while when the two sets are combined the number of detected faults increases. Finally, a new, more efficient architecture for an effective assertion miner has been developed based on the study in this work.enConference Paper10.1109/VLSI-SoC.2019.8920331Other