Gu, XiaoxiongXiaoxiongGuSilberman, Joel A.Joel A.SilbermanYoung, Albert M.Albert M.YoungJenkins, Keith A.Keith A.JenkinsDang, BingBingDangLiu, YongYongLiuDuan, XiaominXiaominDuanGordin, RachelRachelGordinShlafman, ShlomoShlomoShlafmanGoren, DavidDavidGoren2020-05-112020-05-112013-10-30IEEE Transactions on Components, Packaging and Manufacturing Technology 11 (3): Art. 6650001 i.e. Seite 1917-1925 (2013)http://hdl.handle.net/11420/6106Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps (μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design. © 2013 IEEE.en2156-395020131119171925IEEE3-D integrated circuit (IC)3-D integrationOn-chip interconnectSignal integritySubstrate noiseThrough-silicon-via (TSV)TechnikIngenieurwissenschaftenJournal Article10.1109/TCPMT.2013.2264755Other