Kliem, DanielDanielKliemVoigt, Sven-OleSven-OleVoigt2020-10-082020-10-0820132013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013) : Porto, Portugal, 2 - 4 September 2013 ; [proceedings] / [technically co-sponsored by the IEEE Circuits and Systems Society (CAS) and by IEEE. Ed.: João M.P. Cardoso ...]. - Piscataway, NJ : IEEE, 2013. - Art.-Nr. 6645569, Seite 1-4http://hdl.handle.net/11420/7511Recent FPGA families exhibit a bandwidth gap that is inverse to the widely known memory bottleneck of hardwired platforms: Behaviorally described soft processors are comparatively slow whereas FPGAs offer high-throughput state-of-the-art memory attachments. We show that it is possible to take advantage of this bandwidth gap to host functionally partitioned safety- and security-critical software functions. Our proposed multisystem architecture instantiates multiple self-contained local systems on a reconfigurable platform that operates from a shared but partitioned memory. We benchmark and evaluate a novel asynchronous bus bridge and demonstrate that the asynchronous architecture is scalable both at run-time and during place-and-route. © 2013 IEEE.enInformatikAn asynchronous bus bridge for partitioned multi-soc architectures on FPGAsConference Paper10.1109/FPL.2013.6645569Other