Pan, ZhiyaoZhiyaoPanWang, JingJingWangLiu, ShashaShashaLiuLiu, JiayuJiayuLiuSun, WenWenSunLi, QiangQiangLiCheng, LinLinCheng2026-08-072026-08-072026-06-26IEEE Transactions on Circuits and Systems II Express Briefs 73 (8): 808-812 (2026)https://hdl.handle.net/11420/64279This brief presents a compact single-loop discretetime (DT) modulator. The design introduces a dual-phase 2nd-order integrator with a single current-starving floating inverter amplifier (CS-FIA). The charge dissipation and operating point shift during dynamic operation are reduced, as the FIA operates in a relatively stable subthreshold region throughout the entire clock cycle. This enables improved power efficiency across a wide supply voltage range. The ΔΣ modulator is fabricated in a 180 nm CMOS process. It achieves 102.4 dB SNDR at 256 kHz sampling frequency. With a 1.4 V supply, the circuit consumes 8.23 μW, leading to a state-of-the-art Schreier FoM of 183.2 dB. Across a supply voltage range of 1.2 V to 1.6 V, the modulator continuously maintains a FoM above 182 dB.en1558-379120268808812IEEEanalog-to-digital converterdelta–sigma modulatorfloating inverter amplifierlow powermulti-bit quantizerTechnology::621: Applied Physics::621.3: Electrical Engineering, Electronic EngineeringJournal Article10.1109/TCSII.2026.3707609