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Browsing by browse.metadata.journals "ACM transactions on embedded computing systems"

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    Code-inherent traffic shaping for hard real-time systems
    (Association for Computing Machinery, 2019-10)
    Oehlert, Dominic Paul  
    ;
    Saidi, Selma  
    ;
    Falk, Heiko  orcid-logo
    © 2019 Association for Computing Machinery. Modern hard real-time systems evolved from isolated single-core architectures to complex multi-core architectures which are often connected in a distributed manner. With the increasing influence of interconnections in hard real-time systems, the access behavior to shared resources of single tasks or cores becomes a crucial factor for the system's overall worst-case timing properties. Traffic shaping is a powerful technique to decrease contention in a network and deliver guarantees on network streams. In this paper we present a novel approach to automatically integrate a traffic shaping behavior into the code of a program for different traffic shaping profiles while being as least invasive as possible. As this approach is solely depending on modifying programs on a code-level, it does not rely on any additional hardware or operating system-based functions. We show how different traffic shaping profiles can be implemented into programs using a greedy heuristic and an evolutionary algorithm, as well as their influences on the modified programs. It is demonstrated that the presented approaches can be used to decrease worst-case execution times in multi-core systems and lower buffer requirements in distributed systems.
    Publicationtype: Journal Article
    TORE-DOI:10.15480/882.2573
    Citation Publisher Version:ACM Transactions on Embedded Computing Systems 5s (18): a108 1-21 (2019)
    Publisher DOI:10.1145/3358215
    Scopus© Citations 3  336  566
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    Compiling for the worst case : memory allocation for multi-task and multi-core hard real-time systems
    (ACM Press, 2020-03)
    Luppold, Arno  orcid-logo
    ;
    Oehlert, Dominic  
    ;
    Falk, Heiko  orcid-logo
    Modern embedded hard real-time systems feature multiple tasks running on multiple processing cores. Schedulability analysis of such systems is usually performed on an abstract system level with each task being represented as a black box with fixed timing properties. If timing constraints are violated, optimizing the system on a code-level in order to achieve schedulability is a tedious task. To tackle this issue, we propose an extension to the WCET-Aware C Compiler framework WCC. We integrated an optimization framework based on Integer-Linear Programming into the WCC which is able to optimize a multi-core system with multiple tasks running on each core with regards to its schedulability. We evaluate the framework by providing two approaches on a schedulability aware static Scratchpad Memory (SPM) allocation: One based on Integer-Linear Programming (ILP) and one based on a genetic algorithm.
    Publicationtype: Journal Article
    TORE-DOI:10.15480/882.2713
    Citation Publisher Version:ACM Transactions on Embedded Computing Systems 2 (19): 14, 1-26 (2020)
    Publisher DOI:10.1145/3381752
    Scopus© Citations 5  169  408
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    Towards analysing cache-related preemption delay in non-inclusive cache hierarchies
    (Association for Computing Machinery (ACM), 2024-10-05)
    Fischer, Thilo  orcid-logo
    ;
    Falk, Heiko  orcid-logo
    The impact of preemptions has to be considered when determining the schedulability of a task set in a preemptively scheduled system. In particular, the contents of caches can be disturbed by a preemption, thus creating context-switching costs. These context-switching costs occur when a preempted task needs to reload data from memory after a preemption. The additional delay created by this effect is termed cache-related preemption delay (CRPD). The analysis of CRPD has been extensively studied for single-level caches in the past. However, for two-level caches, the analysis of CRPD is still an emerging area of research. In contrast to a single-level cache, which is only affected by direct preemption effects, the second-level cache in a two-level hierarchy can be subject to indirect interference after a preemption. Accesses that could be served from the L1 cache in the absence of preemptions, may be forwarded to the L2 cache, as the relevant data was evicted by a preemption. These accesses create the indirect interference in the L2 cache and can cause further evictions. Recently, a CRPD analysis for two-level non-inclusive cache hierarchies was proposed. In this article, we show that this state-of-the-art analysis is unsafe as it potentially underestimates the CRPD. Furthermore, we show that the analysis is pessimistic and can overestimate the indirect preemption effects. To address these issues, we propose a novel analysis approach for the CRPD in a two-level non-inclusive cache hierarchy. We prove the correctness of the presented approach based on the set of feasible program execution traces. We implemented the presented approach in a worst-case execution time (WCET) analysis tool and compared the performance to existing analysis methods. Our evaluation shows that the presented analysis increases task set schedulability by up to 14 percentage points compared with the state-of-the-art analysis.
    Publicationtype: Journal Article
    TORE-DOI:https://doi.org/10.15480/882.14168
    Citation Publisher Version:ACM Transactions on Embedded Computing Systems 24 (1): 8 (2024)
    Publisher DOI:10.1145/3695768
      5  17
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