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Projekt Titel
Exploration of Power Supply Noise Effects on Maximum Data Rates of High Speed Digital Links in Advanced Server Systems
Startdatum
June 18, 2010
Enddatum
June 17, 2017
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Industry Project.
High speed digital links in IBM’s server systems today are running at data rates of up to 10 Gigabit per second (Gbps). These links are crucial for the overall performance of the system and are carefully designed with respect to signal integrity and bit error rates. The design process follows an iterative procedure in which I/O circuit designers and package designers collectively optimize the link performance using appropriate models for each element of the communication system. As data rates increase in next generation platforms to exceed 12 Gbps, the fundamental noise coupling mechanisms will change making a localized nearest neighbour analysis less relevant. Newer architectures are also increasingly relying on differential links to provide a measure of noise rejection. Increasing data rates will involve new noise coupling mechanisms, many of which are increasingly sensitive to skew, power supply noise, and return current path discontinuities.
The design process for high speed digital links is nowadays focused on the assessment of signal interconnect performance. Power delivery network design is usually a separate effort and its implications for signal quality and maximum achievable data rates are not routinely studied or accurately quantified. In this joint research project the Institute of Electromagnetic Theory in close collaboration with a team from IBM Germany Research & Development explored the effect of power supply noise on the maximum achievable data rates in IBM’s high speed digital links. The team developed successfully a power delivery model for packaging structures and a method for inclusion of simultaneous switching noise into the link budget simulation.
High speed digital links in IBM’s server systems today are running at data rates of up to 10 Gigabit per second (Gbps). These links are crucial for the overall performance of the system and are carefully designed with respect to signal integrity and bit error rates. The design process follows an iterative procedure in which I/O circuit designers and package designers collectively optimize the link performance using appropriate models for each element of the communication system. As data rates increase in next generation platforms to exceed 12 Gbps, the fundamental noise coupling mechanisms will change making a localized nearest neighbour analysis less relevant. Newer architectures are also increasingly relying on differential links to provide a measure of noise rejection. Increasing data rates will involve new noise coupling mechanisms, many of which are increasingly sensitive to skew, power supply noise, and return current path discontinuities.
The design process for high speed digital links is nowadays focused on the assessment of signal interconnect performance. Power delivery network design is usually a separate effort and its implications for signal quality and maximum achievable data rates are not routinely studied or accurately quantified. In this joint research project the Institute of Electromagnetic Theory in close collaboration with a team from IBM Germany Research & Development explored the effect of power supply noise on the maximum achievable data rates in IBM’s high speed digital links. The team developed successfully a power delivery model for packaging structures and a method for inclusion of simultaneous switching noise into the link budget simulation.