PSIC: Priority-Strict Multi-Core IRQ Processing

Publikationstyp
Conference Proceedings
Date Issued
2022-07-06
Sprache
English
Author(s)
Bargholz, Malte  
Dietrich, Christian  orcid-logo
Lohmann, Daniel  
Institut
Operating Systems E-EXK4  
TORE-URI
http://hdl.handle.net/11420/13060
Start Page
1
End Page
9
Citation
25th International Symposium on Real-Time Distributed Computing (2022)
Contribution to Conference
25th International Symposium on Real-Time Distributed Computing 2022  
Publisher DOI
10.1109/ISORC52572.2022.9812796
Scopus ID
2-s2.0-85135369989
ISBN
978-1-6654-0627-7
Peer Reviewed
true
While processing external events, in the form of interrupt requests (IRQs), is a key concern of digital control systems, processing these events can be of different importance for a system’s functionality. Therefore, it is necessary, especially for real-time systems, to ensure that the handling of low-priority IRQs does not interfere with high-priority interrupt-service routines (ISRs) to prevent priority inversions. While prioritizing ISRs on single-core machines is a long-solved problem, priority-strict IRQ handling in multi-core systems is, as we will show, quite challenging with current interrupt controllers.With PSIC, we propose a hardware/software co-design that ensures the priority-strict execution of the top-m ISRs on an m-core machine at minimal interruption-induced overheads. We developed a drop-in replacement for an off-the-shelf interrupt controller that delivers IRQs in strict priority order while achieving low delivering delays at moderate hardware costs. Combined with a minimal IRQ software subsystem, which requires no inter-core synchronization, PSIC guarantees a priority-strict ISR execution on multiple cores.
DDC Class
600: Technik