A low-cost and low-latency inter-stage nonlinearity error calibration algorithm for pipelined ADCs

Yu, Qiang; Li, Qiang

doi:https://doi.org/10.15480/882.16288

A low-cost and low-latency inter-stage nonlinearity error calibration algorithm for pipelined ADCs

Citation Link: https://doi.org/10.15480/882.16288

Basic Data Publication

Publikationstyp

Letter to the Editor

Date Issued

2025-11-26

Sprache

English

Author(s)

Yu, Qiang

Li, Qiang

Integrated Circuits and Systems E-9

TORE-DOI

10.15480/882.16288

TORE-URI

https://hdl.handle.net/11420/59600

Publisher Version

Journal

Electronics letters

Volume

61

Issue

1

Article Number

e70479

Citation

Electronics Letters 61 (1): e70479 (2025)

Publisher DOI

10.1049/ell2.70479

Scopus ID

2-s2.0-105023287457

Publisher

Institution of Engineering and Technology (IET)

Abstract

Pipelined analogue-to-digital converters suffer from inter-stage gain errors and inter-stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial-based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.

Content

Subjects

analogue–digital conversion

calibration

CMOS integrated circuits

DDC Class

621.3: Electrical Engineering, Electronic Engineering

Files

Lizenz

https://creativecommons.org/licenses/by-nc-nd/4.0/

Publication version

publishedVersion

Download

Name

Electronics Letters - 2025 - Yu - A Low‐Cost and Low‐Latency Inter‐Stage Nonlinearity Error Calibration Algorithm for.pdf

Type

Main Article

Size

6.25 MB

Format

Adobe PDF