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A low-cost and low-latency inter-stage nonlinearity error calibration algorithm for pipelined ADCs
Citation Link: https://doi.org/10.15480/882.16288
Publikationstyp
Letter to the Editor
Date Issued
2025-11-26
Sprache
English
TORE-DOI
Journal
Volume
61
Issue
1
Article Number
e70479
Citation
Electronics Letters 61 (1): e70479 (2025)
Publisher DOI
Scopus ID
Publisher
IET
Pipelined analogue-to-digital converters suffer from inter-stage gain errors and inter-stage nonlinearity errors due to gain variations and nonlinearity in residue amplifiers. While a polynomial-based calibration algorithm can address these errors, its conventional implementation demands excessive hardware resources and power consumption. This letter introduces a novel calibration algorithm that combines precomputation with a lookup table, achieving improved hardware efficiency while maintaining calibration accuracy and reducing latency.
Subjects
analogue–digital conversion
calibration
CMOS integrated circuits
DDC Class
621.3: Electrical Engineering, Electronic Engineering
Funding(s)
62090041
Publication version
publishedVersion
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Name
Electronics Letters - 2025 - Yu - A Low‐Cost and Low‐Latency Inter‐Stage Nonlinearity Error Calibration Algorithm for.pdf
Type
Main Article
Size
6.25 MB
Format
Adobe PDF