DRAM cell with high signal charge and small storage capacitance using the gain concept

Publikationstyp
Conference Paper
Date Issued
2000
Sprache
English
Author(s)
Zuckerstaetter, A.
Schloesser, T.
Hofmann, F.
Yuwono, B.
Gschwandtner, A.
Grassl, A.
Innertsberger, G.
Krautschneider, Wolfgang  
Integrierte Schaltungen E-9  
TORE-URI
https://hdl.handle.net/11420/47972
Start Page
196
End Page
199
Article Number
1503678
Citation
In: ESSDERC 2000 : proceedings of the 30th European Solid-State Device Research Conference : Cork, Ireland, 11-13 September 2000. - [Paris?] : Frontier Group, 2000. - S. 196-199
Contribution to Conference
30th European Solid-State Device Research Conference, ESSDERC 2000  
Publisher DOI
10.1109/ESSDERC.2000.194748
Scopus ID
2-s2.0-84907562738
Publisher
Frontier Group
ISBN
2863322486
9782863322482
A new DRAM cell has been developed that features high signal charge and low aspect ratio of the storage capacitor. It can be fabricated based on a standard CMOS process, so that the cell can be integrated into existing technologies. This has been verified by processing of demonstrator cells that provide signal charges greater by factors than as of conventional DRAM cells.
DDC Class
621.3: Electrical Engineering, Electronic Engineering