Asynchronous staggered set/reset techniques for low-noise applications

Start Page
1799
End Page
1802
Article Number
4253009
Citation
2007 IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, USA, 2007, Seite 1799-1802
Contribution to Conference
IEEE International Symposium on Circuits and Systems, ISCAS 2007  
Publisher DOI
10.1109/iscas.2007.378022
Scopus ID
2-s2.0-34548862088
Publisher
IEEE
This work proposes the usage of staggered initialization schemes in digital sequential circuits as complementary technique to reduce the simultaneous switching activity, pursuing the minimization of switching noise levels. Simultaneous switching noise (SSN) generation has been evaluated in digital sequential circuits during initialization and a general synthesis methodology has been proposed in order to implement the staggered initialization schemes at system level. The evaluation of this methodology was made with counter arrays using 0.35μm AMS library cells. In addition, timing considerations, clock suppression during initialization cycles, and the type of cell chosen to implement the staggered distribution are discussed. Main results include noise reduction levels, by suppression of power supply fluctuations, up to 66.7% in post-layout simulations when using staggered techniques enhanced with clock gating during initialization.
DDC Class
621.3: Electrical Engineering, Electronic Engineering