Analysis of a dynamically reconfigurable dataflow architecture and its scalable paralle extension for multi-FPGA platforms

Publikationstyp
Conference Paper
Date Issued
2008
Sprache
English
Author(s)
Voigt, Sven-Ole  
Teufel, Thomas  
Institut
Zuverlässiges Rechnen E-19  
TORE-URI
http://hdl.handle.net/11420/8603
Start Page
261
End Page
262
Citation
International Symposium on Field-Programmable Custom Computing Machines, 2008 : FCCM '08 ; 14 - 15 April 2008, Stanford University, Stanford, Palo Alto, CA / sponsored by IEEE Computer Society Technical Committee on Computer Architecture. Ed. by Kenneth L. Pocek ... - Piscataway, NJ : IEEE, 2008. - ISBN 978-1-4244-4007-8 - ISBN 0-7695-3307-8 - ISBN 978-0-7695-3307-0
Contribution to Conference
16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2008  
Publisher DOI
10.1109/FCCM.2008.27
Scopus ID
2-s2.0-60349106662
Publisher
IEEE
In this paper we analyze a dataflow architecture that maps efficiently onto modern FPGA architectures and is composed of communication channels which can be dynamically adapted to the algorithm's dataflow. The reconfiguration of the architecture's topology can be achieved within a single clock cycle while DSP operations are in progress. In order to maximize the bandwidth, the dataflow channel width is user- definable and can be chosen based on the application- specific requirements. Furthermore, the dataflow architecture can be efficiently mapped onto multi- FPGA platforms increasing at the same time the overall communication bandwidth.
DDC Class
004: Informatik
510: Mathematik