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Efficient design of continuous time linear equalization for loss dominated digital links
Publikationstyp
Conference Paper
Date Issued
2017-06-08
Sprache
English
Institut
TORE-URI
Article Number
7943999
Citation
2017 IEEE 21st Workshop on Signal and Power Integrity, SPI 2017 - Proceedings: 7943999 (2017-06-07)
Contribution to Conference
Publisher DOI
Scopus ID
Publisher
IEEE
Signal degradation in high-speed data links can be mitigated by means of channel equalization. One preferred choice in conjunction with other techniques is the Continuous Time Linear Equalizer (CTLE) due to its effectiveness. Although CTLE being common technology, adaptation of design parameters regularly relies on trial and error. This work proposes a simple, yet very effective method for CTLE design, referred to as matched CTLE (mCTLE). It advocates channel characterization in the frequency domain which is crucial for the placement of CTLE poles and zeros. Demonstration and discussion based on typical interconnect topologies illustrate the novel approach in the context of existing literature.
DDC Class
600: Technik