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Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs
Citation Link: https://doi.org/10.15480/882.1574
Publikationstyp
Journal Article
Date Issued
2013
Sprache
English
Author(s)
Institut
TORE-DOI
Volume
6.2013
Issue
Volume 2013 16 pages
Start Page
Article ID 453173
End Page
16 pages
Citation
Malte Baesler and Sven-Ole Voigt, “Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs,” International Journal of Reconfigurable Computing, vol. 2013, Article ID 453173, 16 pages, 2013. doi:10.1155/2013/453173
Publisher DOI
Scopus ID
Publisher
Hindawi Publishing Corporation
Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binaryand decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.
DDC Class
620: Ingenieurwissenschaften
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