DRAM retention tail improvement by trap passivation

Journal
Solid state electronics  
Volume
51
Issue
11-12
Start Page
1534
End Page
1539
Citation
Solid-State Electronics 51 (11/12): 1534-1539 (2007-11)
Publisher DOI
10.1016/j.sse.2007.09.023
Scopus ID
2-s2.0-36248959235
Publisher
Elsevier
A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512 Mbit and 1 Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40%. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by F-implantation.
DDC Class
621.3: Electrical Engineering, Electronic Engineering