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Efficient simulation framework for circuit design with future device technologies
Publikationstyp
Conference Paper
Date Issued
2004-12-01
Sprache
English
Author(s)
Start Page
385
End Page
388
Citation
In: Proceeding of the 34th European Solid-State Device Research Conference, 2004, ESSDERC 2004 : 21 - 23 Sept. 2004, [Leuven, Belgium]. - Piscataway, NJ : IEEE Operations Center, 2004. - S.385-388
Contribution to Conference
Scopus ID
Publisher
IEEE
ISBN
0780384784
A simulation framework has been developed for fast and accurate calculation of MOS transistor characteristics. It is based on an optimized table model, so that it can be run solely using experimental or simulated I-V data, i.e. without any time-consuming determination of model parameters. This model is designed in a very flexible manner, thus it can be used for advanced MOS structures, such as Double-Gate and FinFET transistors, as well. By this means, it facilitates the integration of a parameterized device technology directly into a conventional design flow to qualify circuits in the design space. ©2004 IEEE.
DDC Class
621.3: Electrical Engineering, Electronic Engineering